EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 86

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–26
Shift Modes
Arria II GX Device Handbook, Volume 1
1
1
The dynamic accum_sload control signal is used to clear the accumulation. A
logic 1 value on the accum_sload signal synchronously loads the accumulator
with the multiplier result only, and a logic 0 enables accumulation by adding or
subtracting the output of the DSP block (accumulator feedback) to the output of the
multiplier and first-stage adder.
The control signal for the accumulator and subtractor is static and therefore must be
configured at compile time.
The multiply accumulate mode supports the round and saturation logic unit because
it is configured as an 18-bit multiplier accumulator.
Arria II GX devices support the following shift modes for 32-bit input only:
■
■
■
■
■
You can switch the shift mode between these modes using the dynamic rotate and
shift control signals.
You can easily use the shift mode in an Arria II GX device with a soft embedded
processor such as the Nios
operation.
Shift mode makes use of the available multipliers to logically or arithmetically shift
left, right, or rotate the desired 32-bit data. The DSP block is configured like the
independent 36-bit multiplier mode to perform the shift mode operations.
The arithmetic shift right requires a signed input vector. During arithmetic shift right,
the sign is extended to fill the MSB of the 32-bit vector. The logical shift right uses an
unsigned input vector. During logical shift right, zeros are padded in the most
significant bits shifting the 32-bit vector to the right. The barrel shifter uses an
unsigned input vector and implements a rotation function on a 32-bit word length.
Two control signals, rotate and shift_right, together with the signa and signb
signals, determine the shifting operation.
Arithmetic shift left, ASL[N]
Arithmetic shift right, ASR[32-N]
Logical shift left, LSL[N]
Logical shift right, LSR[32-N]
32-bit rotator or Barrel shifter, ROT[N]
Figure 4–16
shows the shift mode configuration.
®
II processor to perform the dynamic shift and rotate
Table 4–5
lists examples of shift operations.
Chapter 4: DSP Blocks in Arria II GX Devices
© July 2010 Altera Corporation
Operational Mode Descriptions