EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 182

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–24
Figure 7–16. Arria II GX IOE Input Registers
Notes to
(1) You can bypass each register block in this path.
(2) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(3) This input clock comes from the CQn logic block.
(4) DQS signal must be inverted for DDR interfaces except for QDR II+/QDR II SRAM interfaces. This inversion is done automatically if you use the
Arria II GX Device Handbook, Volume 1
Altera external memory interface IPs.
Figure
DQS (2), (4)
DQSn
CQn (3)
7–16:
DQ
Differential
Buffer
Input
datain
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, and the third register aligns the
captured data. You can choose to use the same clock for the positive edge and
negative edge registers, or two complementary clocks (DQS/CQ for positive-edge
register and DQSn/CQn for negative-edge register). The third register that aligns the
captured data uses the same clock as the positive edge registers.
The resynchronization registers resynchronize the data to the resynchronization clock
domain. These registers are clocked by the resynchronization clock that is generated
by the PLL. The outputs of the resynchronization registers go straight to the core.
1
0
Double Data Rate Input Registers
Input Reg B
Input Reg A
D
D
DFF
DFF
Resynchronization
Clock
(resync_clk_2x)
(3)
Q
Q
neg_reg_out
I
I
regouthi
(Note 1)
Input Reg C
D
DFF
Q
I
regoutlo
Synchronization Registers
D
D
Chapter 7: External Memory Interfaces in Arria II GX Devices
DFF
DFF
Q
Q
Arria II GX External Memory Interface Features
© July 2010 Altera Corporation
To Core (rdata0)
To Core (rdata1)