EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 16

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–2
Table 1–1. Arria II GX Device Features (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
Total Transceivers
ALMs
LEs
PCIe hard IP blocks
M9K Blocks
Total Embedded Memory in M9K
Blocks (Kbits)
Total On-Chip Memory (M9K + MLABs)
(Kbits)
Embedded Multipliers (18 × 18)
General Purpose PLLs
Feature
■
■
■
■
Table 1–1
Optimized for high-bandwidth system interfaces
■
■
Low power
■
■
■
Advanced usability and security features
■
■
■
■
■
Emulated LVDS output support with a data rate of up to 945 Mbps
Up to 612 user I/O pins arranged in up to 12 modular I/O banks that support a
wide range of single-ended and differential I/O standards
High-speed LVDS I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to
1.25 Gbps
Patented architectural power reduction techniques
Per-channel transceiver power consumption is approximately 100 mW under
typical conditions at 3.125 Gbps
Power optimizations integrated into the Quartus II development software
Parallel and serial configuration options
On-chip series termination (R
256-bit advanced encryption standard (AES) programming file encryption for
design security with volatile and non-volatile key storage options
Robust portfolio of IP for processing, serial protocols, and memory interfaces
Low cost, easy-to-use development kits featuring high-speed mezzanine
connectors (HSMC)
(1)
lists Arria II GX device features.
EP2AGX45
18,050
42,959
2,871
3,435
319
232
8
1
4
EP2AGX65
25,300
60,214
4,455
5,246
495
312
8
1
4
S
OCT) and differential I/O termination
EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260
37,470
89,178
5,508
6,679
612
448
12
1
6
Chapter 1: Arria II GX Device Family Overview
118,143
49,640
6,570
8,121
730
576
12
1
6
© July 2010 Altera Corporation
181,165
76,120
7,560
9,939
840
656
16
1
6
102,600
244,188
11,756
8,550
950
736
16
Highlights
1
6