EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 124

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–32
Figure 5–25. PLL Reconfiguration Waveform
Arria II GX Device Handbook, Volume 1
CONFIGUPDATE
SCANDATAOUT
SCANCLKENA
SCANDONE
SCANDATA
SCANCLK
ARESET
1
Dn_old
To reconfigure the PLL counters, follow these steps:
1. Assert the scanclkena signal at least one scanclk cycle prior to shifting in the
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 180 bits are scanned into the scan chain, the scanclkena signal is
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high indicating the PLL is being reconfigured. A falling
6. Reset the PLL with the areset signal if you make any changes to the M, N, or
7. Repeat steps
Figure 5–25
When you reconfigure the counter clock frequency, you cannot reconfigure the
corresponding counter phase shift settings with the same interface. Instead,
reconfigure the phase shifts in real time with the dynamic phase shift reconfiguration
interface. If you reconfigure the counter frequency, but want to keep the same
non-zero phase shift setting (for example, 90°) on the clock output, you must
reconfigure the phase shift immediately after reconfiguring the counter clock
frequency.
Post-Scale Counters (C0 to C6)
You can configure the multiply or divide values and duty cycle of post-scale counters
in real time. Each counter has an 8-bit high-time setting and an 8-bit low-time setting.
The duty cycle is the ratio of output high- or low-time to the total cycle time, which is
the sum of the two. Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty cycle.
first bit of scandata (Dn).
scanclk.
deasserted to prevent inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
edge indicates the PLL counters are updated with new settings.
post-scale output C counters or the Icp, R, or C settings.
Dn
shows a functional simulation of the PLL reconfiguration feature.
1
through
5
to reconfigure the PLL any number of times.
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
D0_old
D0
Dn
© July 2010 Altera Corporation
PLLs in Arria II GX Devices