EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 279

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Design Security
Security Modes Available
© July 2010
Altera Corporation
1
Figure 9–29. Design Security
Note to
(1) Step 1, Step 2, and Step 3 correspond to the procedure detailed in
The following sections describe the security modes available on Arria II GX devices.
Volatile Key
Secure operation with volatile key programmed and required external battery—this
mode accepts both encrypted and unencrypted configuration bitstreams. Use the
unencrypted configuration bitstream support for board-level testing only.
Non-Volatile Key
Secure operation with one-time-programmable (OTP) security key programmed—
this mode accepts both encrypted and unencrypted configuration bitstreams. Use the
unencrypted configuration bitstream support for board level testing only.
Volatile Key with Tamper Protection Bit Set
Secure operation in tamper resistant mode with volatile security key programmed—
only encrypted configuration bitstreams are allowed to configure the device. Tamper
protection disables JTAG configuration with unencrypted configuration bitstream.
Enabling the Tamper Protection bit disables the test mode in Arria II GX devices. This
process is irreversible and prevents Altera from carry-out failure analysis. Contact
Altera Technical Support to enable the tamper protection bit.
Figure
9–29:
User-Defined
Configuration
Encrypted
AES Key
File
(Note 1)
Step 2
Step 1
“Design Security” on page
Configuration
Arria II GX FPGA
Arria II GX Device Handbook, Volume 1
Memory or
Key Storage
Decryption
Device
AES
Step 3
9–55.
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