EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 244

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–24
Figure 9–12. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to
Arria II GX Device Handbook, Volume 1
to meet the V
systems I/Os with V
page
Figure
9–7.
(MAX II Device or
Microprocessor)
External Host
ADDR
9–12:
IH
Memory
specification of the I/O standard on the device and the external host. Altera recommends that you power up all configuration
DATA[0]
CCIO
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. All other configuration pins (nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices start and
complete configuration at the same time.
Figure 9–12
receiving the same configuration data.
for I/O bank 3C.
V
CCIO (1)
shows multi-device PS configuration when both Arria II GX devices are
10 k Ω
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
V
CCIO (1)
10 k Ω
GND
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Arria II GX Device
MSEL[3..0]
nCEO
N.C.
(2)
GND
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
© July 2010 Altera Corporation
Arria II GX Device
Passive Serial Configuration
CCIO
MSEL[3..0]
must be high enough
nCEO
Table 9–2 on
N.C.
(2)