EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 71

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II GX Devices
DSP Block Resource Descriptions
Pipeline Register Stage
Second-Stage Adder
© July 2010
Altera Corporation
1
Table 4–4. Multiplier Sign Representation
Each half block has its own signa and signb signal. Therefore, all data A inputs
feeding the same half-DSP block must have the same sign representation. Similarly, all
data B inputs feeding the same half-DSP block must have the same sign
representation. The multiplier offers full precision regardless of the sign
representation in all operational modes except for full precision 18 × 18 loopback and
two-multiplier adder modes. For more information, refer to
Sum Mode” on page
When signa and signb signals are unused, the Quartus II software sets the
multiplier to perform unsigned multiplication by default.
The outputs of the multipliers are the only outputs that can feed into the first-stage
adder, as shown in
block (two adders per half-DSP block). The first-stage adder block has the ability to
perform addition and subtraction. The control signal for addition or subtraction is
static and has to be configured upon compile time. The first-stage adders are used by
the sum modes to compute the sum of two multipliers, 18 × 18-complex multipliers,
and to perform the first stage of a 36 × 36 multiply and shift operation.
Depending on your specifications, the output of the first-stage adder has the option to
feed into the pipeline registers, second-stage adder, round and saturation unit, or the
output registers.
The output from the first-stage adder can either feed or bypass the pipeline registers,
as shown in
performance (at the expense of extra cycles of latency) of the DSP block, especially
when using the subsequent DSP block stages. Pipeline registers split up the long
signal path between the input-registers/multiplier/first-stage adder and the
second-stage adder/round-and-saturation/output-registers, creating two shorter
paths.
There are four individual 44-bit second-stage adders per DSP block (two adders per
half-DSP block). You can configure the second-stage adders as follows:
■
■
■
■
The final stage of a 36-bit multiplier
A sum of four (18 × 18)
An accumulator (44-bits maximum)
A chained output summation (44-bits maximum)
Data A (signa Value)
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
Figure 4–4 on page
Figure 4–4 on page
4–20.
4–7. Pipeline registers increase the maximum
4–7. There are four first-stage adders in a DSP
Data B (signb Value)
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
Arria II GX Device Handbook, Volume 1
“Two-Multiplier Adder
Unsigned
Result
Signed
Signed
Signed
4–11