EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 256

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–36
Table 9–11. Dedicated Configuration Pins on the Arria II GX Device (Part 1 of 4)
Arria II GX Device Handbook, Volume 1
VCCPD
nIO_PULLUP
MSEL[3..0]
nCONFIG
Pin Name
User Mode
N/A
N/A
N/A
N/A
Table 9–11
properly on your board for successful configuration. Some of these pins may not be
required for your configuration schemes.
Configuration
Scheme
lists the dedicated configuration pins. You must connect these pins
All
All
All
All
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Pin Type
Power
Input
Input
Input
Dedicated power pin. Use this pin to power the I/O
pre-drivers, the HSTL/SSTL input buffers, and the
MSEL[3..0].
You must connect V
the same bank:
■
■
■
V
100 ms (for standard POR) or 4 ms (for fast POR). If V
not ramped up in this specified time, your Arria II GX device is
not successfully configured.
Dedicated input that chooses whether the internal pull-up
resistors on the user I/O pins and dual-purpose I/O pins
(DATA[1:7], CLKUSR, INIT_DONE, DEV_OE, and
DEV_CLRn) are on or off before and during configuration. A
logic high turns off the weak internal pull-up resistors, while a
logic low turns them on.
The nIO-PULLUP input buffer is powered by V
internal 5-kpull-down resistor that is always active. You can
tie the nIO-PULLUP directly to the V
bank in which the pin resides or GND.
Four-bit configuration input that sets the Arria II GX device
configuration scheme. For the appropriate connections, refer
to
You must hardwire these pins to the V
The MSEL[3..0] pins have internal 5-k pull-down
resistors that are always active.
Configuration control input. Pulling this pin low during
user-mode causes the device to lose its configuration data,
enter a reset state, and tri-state all I/O pins. Returning this pin
to a logic-high level starts a reconfiguration.
Configuration is possible only if this pin is high, except in
JTAG programming mode, when nCONFIG is ignored.
CCPD
Table 9–2 on page
For 3.3-V I/O standards, connect V
For 3.0-V I/O standards, connect V
For 2.5-V and below I/O standards, connect V
must ramp up from 0 V to 2.5 V, 3.0 V, or 3.3 V in
CC PD
9–7.
according to the I/O standard used in
Description
© July 2010 Altera Corporation
CC PD
CC PD
CCIO
CC PD
Device Configuration Pins
to 3.3 V
to 3.0 V
power supply of the
or GND.
CC
CC PD
and has an
to 2.5 V
CCPD
is