EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 159

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

© July 2010 Altera Corporation
AIIGX51007-3.0
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1
This chapter describes the hardware features in Arria
high-speed memory interfacing for the double data rate (DDR) memory standard
including delay-locked loops (DLLs). Memory interfaces also use I/O features such as
on-chip termination (OCT), programmable input delay chains, programmable output
delay, slew rate adjustment, and programmable drive strength.
Arria II GX devices provide an efficient architecture to quickly and easily fit wide
external memory interfaces with their small modular I/O bank structure. The I/Os
are designed to provide flexible and high-performance support for existing and
emerging external DDR memory standards, such as DDR3, DDR2, DDR SDRAM,
QDR II, and QDR II+ SRAM. The Arria II GX FPGA supports DDR external memory
on the top, bottom, and right I/O banks.
The high-performance memory interface solution includes the self-calibrating
ALTMEMPHY megafunction and UniPHY Intellectual Property (IP) core, optimized
to take advantage of the Arria II GX I/O structure and the Quartus
Timing Analyzer. The ALTMEMPHY megafunction and UniPHY IP core provide the
total solution for the highest reliable frequency of operation across process, voltage,
and temperature (PVT) variations.
The ALTMEMPHY megafunction and UniPHY IP core instantiate a phase-locked loop
(PLL) and PLL reconfiguration logic to adjust the resynchronization phase shift based
on PVT variation.
This chapter includes the following sections:
■
■
■
For Arria II GX devices, the Quartus II software version 10.0 only has support for
QDR II and QDR II + SRAM controller with UniPHY IP core.
For more information about any of the above-mentioned features, refer to the
Features in Arria II GX Devices
For more information about external memory system specifications, implementation,
board guidelines, timing analysis, simulation, debug information, ALTMEMPHY
megafunction and UniPHY IP core support for Arria II GX devices, refer to the
External Memory Interface
For more information about the Arria II GX PLL, refer to the
in Arria II GX Devices
“Arria II GX Memory Interfaces Pin Support”
“Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface”
on page 7–13
“Arria II GX External Memory Interface Features” on page 7–14
chapter.
Handbook.
chapter.
7. External Memory Interfaces in
®
II GX devices that facilitate
Arria II GX Devices
Arria II GX Device Handbook, Volume 1
Clock Networks and PLLs
®
II TimeQuest
I/O