EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 67

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II GX Devices
DSP Block Resource Descriptions
Figure 4–4. Half-DSP Block Architecture
Notes to
(1) Block output for accumulator overflow and saturate overflow.
(2) Block output for saturation overflow of chainout.
(3) When the chainout adder is not in use, the second adder register banks are known as output register banks.
(4) You must connect the chainin port to the chainout port of the previous DSP blocks; it must not be connected to general routings.
Input Registers
© July 2010
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_3[ ]
datab_1[ ]
dataa_2[ ]
datab_2[ ]
dataa_3[ ]
chainin[ ]
Figure
scanina[ ]
Altera Corporation
(4)
4–4:
loopback
scanouta
Figure 4–4
Table 4–9 on page 4–30
All DSP block registers are triggered by the positive edge of the clock signal and are
cleared upon power up. Each multiplier operand can feed an input register or feed
directly to the multiplier, bypassing the input registers. The following DSP block
signals control the input registers in the DSP block:
■
■
■
clock[3..0]
ena[3..0]
alcr[3..0]
clock[3..0]
ena[3..0]
aclr[3..0]
Half-DSP Block
shows a detailed overall architecture of the top half of the DSP block.
chainout_saturate
chainout_round
zero_loopback
zero_chainout
accum_sload
lists the DSP block dynamic signals.
output_saturate
(3)
output_round
shift_right
rotate
signa
signb
Arria II GX Device Handbook, Volume 1
chainout
overflow (1)
chainout_sat_overflow (2)
result[ ]
4–7