EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 15

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Highlights
© July 2010 Altera Corporation
AIIGX51001-3.0
The Arria
cost-optimized, 40-nm device family architecture features a low-power,
programmable logic engine and streamlined transceivers and I/Os. Common
interfaces, such as the Physical Interface for PCI Express
and DDR3 memory are easily implemented in your design with the Quartus
software, the SOPC Builder design software, and a broad library of hard and soft
intellectual property (IP) solutions from Altera
designing for applications requiring transceivers operating at up to 6.375 Gbps fast
and easy.
This chapter contains the following sections:
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The Arria II GX device features consist of the following highlights:
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“Highlights”
“Arria II GX Device Architecture” on page 1–4
“Reference and Ordering Information” on page 1–11
40-nm, low-power FPGA engine
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High-performance digital signal processing (DSP) blocks up to 380 MHz
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Maximum system bandwidth
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Complete PIPE protocol solution with an embedded hard IP block that provides
physical interface and media access control (PHY/MAC) layer, Data Link layer,
and Transaction layer functionality
Adaptive logic module (ALM) offers the highest logic efficiency in the industry
Eight-input fracturable look-up table (LUT)
Memory logic array blocks (MLABs) for efficient implementation of small
FIFOs
Configurable as 9 × 9-bit, 12 × 12-bit, 18 × 18-bit, and 36 × 36-bit full-precision
multipliers as well as 18 × 36-bit high-precision multiplier
Hardcoded adders, subtractors, accumulators, and summation functions
Fully-integrated design flow with the MATLAB and DSP Builder software
from Altera
Up to 16 full-duplex clock data recovery (CDR)-based transceivers supporting
rates between 155 Mbps and 6.375 Gbps
Dedicated circuitry to support physical layer functionality for popular serial
protocols, including PCIe Gen1, Gbps Ethernet, Serial RapidIO
Common Public Radio Interface (CPRI), OBSAI, SD/HD/3G/ASI Serial
Digital Interface (SDI), XAUI, HiGig/HiGig+, SATA/Serial Attached SCSI
(SAS), GPON, SerialLite II, Fiber Channel, and SONET/SDH
®
II GX device family is designed specifically for ease-of-use. The
1. Arria II GX Device Family Overview
®
. The Arria II GX device family makes
®
(PIPE) (PCIe
Arria II GX Device Handbook, Volume 1
®
®
(SRIO),
), Ethernet,
®
II