EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 81

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II GX Devices
Operational Mode Descriptions
Figure 4–12. Loopback Mode for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
© July 2010
Figure
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
Altera Corporation
4–12:
1
zero_loopback
If all the inputs are full 18-bit and unsigned, the result requires 37 bits for
two-muliplier adder mode. Because the output data width in two-multiplier adder
mode is limited to 36 bits, this 37-bit output requirement is not allowed. Any other
combination that does not violate the 36-bit maximum result is permitted; for
example, two 16 × 16 signed two-multiplier adders is valid.
Two-multiplier adder mode supports the round and saturation logic unit. You can use
pipeline registers and output registers in the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
18 × 18 Complex Multiplier
You can configure the DSP block to implement complex multipliers using the
two-multiplier adder mode. A single half-DSP block can implement one 18-bit
complex multiplier.
Half-DSP Block
loopback
clock[3..0]
ena[3..0]
aclr[3..0]
output_saturate
+
output_round
signa
signb
Arria II GX Device Handbook, Volume 1
overflow (1)
result[ ]
4–21