EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 17

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Arria II GX Device Family Overview
Highlights
Table 1–1. Arria II GX Device Features (Part 2 of 2)
Table 1–2. Package Options and I/O Information for Arria II GX Devices
© July 2010 Altera Corporation
Transceiver TX PLLs
User I/O Banks
Notes to
(1) This is in four multiplier adder mode.
(2) The FPGA fabric can use these phase locked-loops (PLLs) if they are not used by the transceiver.
(3) The number of PLLs depends on the package. Transceiver transmitter (TX) PLL count = (number of transceiver blocks)
(4) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
Notes to
(1) The user I/O counts include clock pins.
(2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,
(3) R
(4) RX = True LVDS input buffers without R
(5) TX = True LVDS output buffers.
(6) eTX = Emulated-LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
Device
and power pins are the same for a given package across device densities.
D
= True LVDS input buffers with on-chip differential termination (R
Table
Table
1–1:
1–2:
156
156
I/O
Feature
(4)
—
—
—
—
358-Pin Flip Chip UBGA
17 mm × 17 mm
(2)
33(R
33(R
+ 32(RX, TX,
+ 32(RX, TX,
Table 1–2
high-speed LVDS channel counts, and transceiver channel counts for ultra BGA
(UBGA) and FineLine BGA (FBGA) devices.
or eTX)
or eTX)
LVDS
D
D
—
—
—
—
or eTX)
or eTX)
lists the Arria II GX device package options and user I/O pin counts,
D
—
—
—
—
OCT support.
4
4
EP2AGX45
2 or 4
252
252
260
260
I/O
—
—
572-Pin Flip Chip FBGA
6
(3)
25 mm × 25 mm
57(R
57(R
57(R
57(R
+ 56(RX, TX,
+ 56(RX, TX,
+ 56(RX, TX,
+ 56(RX,TX,
or eTX)
or eTX)
or eTX)
or eTX)
LVDS
EP2AGX65
D
D
D
D
2 or 4
—
—
or eTX)
or eTX)
or eTX)
or eTX)
6
D
(3)
OCT) support.
—
—
8
8
8
8
EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260
4 or 6
364
364
372
372
372
372
8
(Note
I/O
780-Pin Flip Chip FBGA
(3)
29 mm × 29 mm
85(R
1), (2),
+84(RX, TX, or
+84(RX, TX, or
+84(RX, TX, or
+84(RX,TX, or
85(R
85(R
85(R
85(R
84(RX, TX, or
85(R
+84(RX,TX,
4 or 6
D
LVDS
eTX)
eTX)
eTX)
eTX)
eTX)
eTX)
D
D
D
D
or eTX) +
D
or eTX)
or eTX)
or eTX)
or eTX)
, eTX)
(3), (4), (5), (6), (7)
8
(3)
Arria II GX Device Handbook, Volume 1
6 or 8
12
12
12
12
8
8
12
452
452
612
612
(3)
I/O
—
—
1152-Pin Flip Chip FBGA
×
2.
35 mm × 35 mm
105(R
105(R
145(R
145(R
144(RX, TX, or
+ 104(RX, TX,
+ 104(RX, TX,
+ 144(RX, TX,
6 or 8
or eTX)
or eTX)
or eTX)
LVDS
eTX)
12
D
D
D
D
—
—
, eTX) +
or eTX)
or eTX)
or eTX)
(3)
1–3
—
—
12
12
16
16