EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 122
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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5–30
Figure 5–23. VCO Switchover Operating Frequency
PLL Reconfiguration
Arria II GX Device Handbook, Volume 1
ΔF vco
■
■
The PLLs use several divide counters and different VCO phase taps to perform
frequency synthesis and phase shifts. In Arria II GX PLLs, you can reconfigure both
the counter settings and phase-shift the PLL output clock in real time. You can also
change the charge pump and loop-filter components, which dynamically affect the
PLL bandwidth. You can use these PLL components to update the output-clock
frequency and the PLL bandwidth and to phase shift in real time, without
reconfiguring the entire Arria II GX device.
The ability to reconfigure the PLL in real time is useful in applications that operate at
multiple frequencies. It is also useful in prototyping environments, allowing you to
sweep PLL output frequencies and adjust the output-clock phase dynamically. For
instance, a system generating test patterns is required to generate and transmit
patterns at 75 or 150 MHz, depending on the requirements of the device under test.
Reconfiguring the PLL components in real time allows you to switch between two
such output frequencies in a few microseconds. You can also use this feature to adjust
clock-to-out (t
This approach eliminates the requirement to regenerate a configuration file with the
new PLL settings.
Figure 5–23
clock is lost and then increases as the VCO locks on to the backup clock.
Disable the system during clock switchover if it is not tolerant of frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1] status signals to turn off the PFD (PFDENA = 0) so the VCO
maintains its most recent frequency. You can also use the state machine to switch
over to the secondary clock. When the PFD is reenabled, output clock-enable
signals (clkena) can disable the clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
reenable the output clocks.
Primary Clock Stops Running
CO
shows how the VCO frequency gradually decreases when the current
) delays in real time by changing the PLL output clock phase shift.
Switchover Occurs
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
VCO Tracks Secondary Clock
© July 2010 Altera Corporation
PLLs in Arria II GX Devices
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