EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 269

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EP2AGX65DF29C6N

Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX65DF29C6N

Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Dedicated Remote System Upgrade Circuitry
Dedicated Remote System Upgrade Circuitry
© July 2010
Altera Corporation
If there is an error while loading the application configuration, the cause of the
reconfiguration is written by the dedicated circuitry to the remote system upgrade
status register. Actions that cause the remote system upgrade status register to be
written are:
Arria II GX devices automatically load the factory configuration located at page
address zero. This user-designed factory configuration can read the remote system
upgrade status register to determine the reason for the reconfiguration. The factory
configuration then takes appropriate error recovery steps and writes to the remote
system upgrade control register to determine the next application configuration to be
loaded.
When Arria II GX devices successfully load the application configuration, they enter
into user mode. In user mode, the soft logic (Nios II processor or state machine and
the remote communication interface) assists the Arria II GX device in determining
when a remote system update is arriving. When a remote system update arrives, the
soft logic receives the incoming data, writes it to the configuration memory device,
and triggers the device to load the factory configuration. The factory configuration
reads the remote system upgrade status register and control register, determines the
valid application configuration to load, writes the remote system upgrade control
register accordingly, and initiates system reconfiguration.
This section describes the implementation of the Arria II GX dedicated remote system
upgrade circuitry. The remote system upgrade circuitry is implemented in hard logic.
This dedicated circuitry interfaces with the user-defined factory and application
configurations implemented in the Arria II GX device logic array to provide the
complete remote configuration solution. The remote system upgrade circuitry
contains the remote system upgrade registers, a watchdog timer, and a state machine
that controls those components.
nSTATUS driven low externally
Internal CRC error
User watchdog timer time-out
A configuration reset (logic array nCONFIG signal or external nCONFIG pin
assertion to low)
Arria II GX Device Handbook, Volume 1
9–49

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