EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 292

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–8
Arria II GX Device Handbook, Volume 1
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to
where n is between 1 and 8. The divisor ranges from 2 through 256 (refer to
Equation
Equation 10–1.
The error message register is updated whenever an error occurs. If the error location
and message are not shifted out before the next error location is found, the previous
error location and message is overwritten by the new information. To avoid this, you
must shift these bits out within one frame CRC verification. The minimum interval
time between each update for the error message register depends on the device and
the error detection clock frequency. However, slowing down the error detection clock
frequency slows down the error recovery time for the SEU event.
Table 10–7
error message register for Arria II GX devices.
Table 10–7. Minimum Update Interval for Error Message Register
1
10–1).
The error detection frequency reflects the frequency of the error detection
process for a frame because the CRC calculation in Arria II GX devices is
done on a per-frame basis.
lists the estimated minimum interval time between each update for the
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX95
“Software Support” on page
Device
error detection frequency
10–9). The divisor is a power of two (2),
=
Chapter 10: SEU Mitigation in Arria II GX Devices
100MHz
------------------- -
2
n
Timing Interval (s)
© July 2010 Altera Corporation
11.04
11.04
14.88
14.88
19.64
19.64
Error Detection Timing