EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 94

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–2
Global Clock Networks
Figure 5–1. GCLK Networks
Notes to
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins.
Regional Clock Networks
Arria II GX Device Handbook, Volume 1
Figure
Top Left PLL
Bottom Left PLL
5–1:
Arria II GX devices provide up to 16 GCLKs that can drive throughout the device,
serving as low-skew clock sources for functional blocks such as adaptive logic
modules (ALMs), digital signal processing (DSP) blocks, embedded memory blocks,
and PLLs. Arria II GX I/O elements (IOEs) and internal logic can also drive GCLKs to
create internally generated GCLKs and other high fan-out control signals; for
example, synchronous or asynchronous clears and clock enables.
CLK pins and PLLs that can drive GCLK networks in Arria II GX devices.
The RCLK networks only pertain to the quadrant they drive into. Arria II GX devices
contain 48 RCLK networks that provide the lowest clock delay and skew for logic
contained in a single device quadrant. Arria II GX IOEs and internal logic in a given
quadrant can also drive RCLKs to create internally generated RCLKs and other high
fan-out control signals; for example, synchronous or asynchronous clears and clock
enables.
Arria II GX devices.
PLL_4
PLL_1
GCLK[0..3] ( 2 )
Figure 5–2
shows CLK pins and PLLs that can drive RCLK networks in
GCLK[12..15]
GCLK[4..7]
CLK[4..7]
CLK[12..15]
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
GCLK[8..11]
Clock Networks in Arria II GX Devices
PLL_2
PLL_5
PLL_6
PLL_3
© July 2010 Altera Corporation
Bottom Right PLL
(1)
(1)
Figure 5–1
Top Right PLL
Center PLLs
CLK[8..11]
shows