EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 145

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II GX Devices
Arria II GX OCT Support
Table 6–5. Arria II GX MultiVolt I/O Support
Arria II GX OCT Support
© July 2010 Altera Corporation
Notes to
(1) The pin current may be slightly higher than the default value. You must verify that the driving device’s V
(2) Each I/O bank of an Arria II GX Device has its own VCCIO pins and supports only one V
(3) Altera recommends using an external clamp diode on the column I/O pins when the input signal is 3.0 V or 3.3 V.
VCCIO (V)
do not violate the applicable Arria II GX V
I/O standard is not supported when V
output operations are only supported when V
1.2
1.5
1.8
2.5
3.0
3.3
(2)
Table
6–5:
1
1.2
v
—
—
—
—
—
Arria II GX devices feature R
termination capabilities. OCT maintains signal quality, saves board space, and
reduces external component costs.
Arria II GX devices support R
differential termination for differential LVDS I/O standards. Arria II GX devices
support OCT in all user I/O banks by selecting one of the OCT I/O standards.
Arria II GX devices support R
standards if they use the same V
each I/O in an I/O bank to support R
You cannot configure both R
I/O buffer.
A pair of RUP and RDN pins are available in a given I/O bank for series calibrated
termination. RUP and RDN pins share the same V
I/O bank where they are located. RUP and RDN pins are dual-purpose I/Os, and
function as regular I/Os if you do not use the calibration circuit. When used for
calibration, RUP and RDN pins are connected to V
external 25- ±1% or 50- ±1% resistor for a R
respectively.
On-Chip Series Termination without Calibration
Arria II GX devices support driver-impedance matching to provide the I/O driver
with controlled output impedance that closely matches the impedance of the
transmission line. As a result, you can significantly reduce reflections. Arria II GX
devices support R
The R
typical R
1.5
—
v
v
—
—
—
S
shown in
Input Signal (V)
S
1.8
v
v
—
—
—
—
values are 25  and 50  .
CCIO
IL
is 3.0 V. The LVDS input operations are supported when V
maximum and V
CCIO
Figure 6–3
2.5
v
v
v
S
—
—
—
(Note 1)
OCT for single-ended I/O standards.
is 2.5 V.
v
v
v
3.0
—
—
—
IH
(3)
(3)
(3)
is the intrinsic impedance of output transistors. The
minimum voltage specifications.
S
S
S
S
OCT and programmable current strength for the same
OCT to provide I/O impedance matching and
OCT with or without calibration, and on-chip
OCT in the same I/O bank with different I/O
v
v
CCIO
v
3.3
—
—
—
(3)
(3)
(3)
supply voltage. You can independently configure
S
OCT or programmable current strength.
1.2
v
—
—
—
—
—
S
CCIO
OCT value of 25  or 50  ,
CCIO
CCIO
, either 1.2, 1.5, 1.8, 2.5, 3.0, or 3.3 V. The LVDS
1.5
—
v
—
—
—
—
or GND, respectively, through an
and GND, respectively, with the
Output Signal (V)
CCIO
OL
Arria II GX Device Handbook, Volume 1
maximum and V
is 1.2, 1.5, 1.8, or 2.5 V. The LVDS
1.8
v
—
—
—
—
—
2.5
v
—
—
—
—
—
OH
minimum voltages
3.0
v
—
—
—
—
—
3.3
v
—
—
—
—
—
6–11