EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 199

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Receiver
Figure 8–12. Receiver Datapath in DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively.
(3) The rx_out port has a maximum data width of 10.
© July 2010
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Altera Corporation
8–12:
10
DPA Mode
In DPA mode, the DPA circuitry automatically chooses the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for the
skew between the two signals. The reference clock must be a differential signal.
Figure 8–12
DPA_diffioclk clock to write serial data into the synchronizer. Use the
LVDS_diffioclk clock to read the serial data from the synchronizer. Use the same
LVDS_diffioclk clock in the data realignment and deserializer blocks.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the DPA mode receiver datapath block diagram. Use the
IOE
Center/Corner PLL
2
(Note
3
DOUT DIN
Multiplier
Bit Slip
Clock
(LVDS_LOAD_EN,
LVDS_diffioclk,
1), (2),
rx_outclk)
diffioclk
(3)
rx_inclock
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
Arria II GX Device Handbook, Volume 1
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
Data
DPA Clock
DPA Circuitry
DIN
+
LVDS Clock Domain
DPA Clock Domain
rx_in
8–15