EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 25

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Arria II GX Device Family Overview
Reference and Ordering Information
SEU Mitigation
JTAG Boundary Scan Testing
Reference and Ordering Information
© July 2010 Altera Corporation
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Figure 1–2
Figure 1–2. Packaging Ordering Information Arria II GX Devices
Transceiver Count
F: FineLine BGA (FBGA)
U: Micro BGA (UFBGA)
C: 4
D: 8
E: 12
F:16
EP2AGX
125, 190, 260
Offers built-in error detection circuitry to detect data corruption due to soft errors
in the configuration random access memory (CRAM) cells
Allows all CRAM contents to be read and verified to match a
configuration-computed cyclic redundancy check (CRC) value
You can identify and read out the bit location and the type of soft error through the
JTAG or the core interface
Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications
IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers and
performs boundary scan on alternating current (AC)-coupled transceiver channels
Boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and capture functional data while a device is
operating normally
Device Density
Package Type
Family S i g n a t u r e
45, 65, 95
describes the ordering codes for Arria II GX devices.
EP2AGX
45
C
F
Ball Array Dimension
Corresponds to pin count
17 = 358 pins
25 = 572 pins
29 = 780 pins
35 = 1152 pins
17
C
4
N
Indicates specific device shipment method
ES: Engineering sample
N: Lead-free devices
Optional Suffix
3, 4, 5, or 6, with 3 being the fastest
C: Commercial temperature (t
I: Industrial temperature (t
Arria II GX Device Handbook, Volume 1
Speed Grade
Operating Temperature
J
= -40°C to 100°C)
J
= 0°C to 85°C)
1–11