EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 202

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–18
Differential I/O Termination
PLLs
Arria II GX Device Handbook, Volume 1
Table 8–3
emphasis in the Quartus II software Assignment Editor.
Table 8–3. Programmable Pre-Emphasis Settings in Quartus II Software Assignment Editor
There is one V
name and value for programmable V
Table 8–4. Programmable V
The Arria II GX devices provide 100- R
top, right, and bottom I/O banks. OCT saves board space by not adding external
resistors on the board. You can enable OCT in the Quartus II software Assignment
Editor.
Figure 8–15
OCT.
Figure 8–15. LVDS Input Buffer On-Chip Differential I/O Termination
Table 8–5
termination in the Quartus II software Assignment Editor.
Table 8–5. On-Chip Differential Input Termination in Quartus II Software Assignment Editor
The Arria II GX devices contain up to six PLLs with up to four center and corner PLLs
located on the right side of the device. Use the center/corner PLL on the right side of
the device to generate parallel clocks (rx_outclock and tx_outclock) and
high-speed clocks (diffioclk) for the SERDES and DPA circuitry.
page 8–3
and dynamic reconfiguration are allowed using the center/corner PLLs in high-speed
differential I/O support mode.
Programmable Pre-Emphasis
Programmable Differential Output Voltage (V
Input Termination (Accepts wildcards/groups)
shows the locations of the PLLs for Arria II GX devices. Clock switchover
lists the assignment name and its possible values for programmable pre-
lists the assignment name and its value for on-chip differential input
shows LVDS input OCT. Clock input pins (CLK[4..15]) do not support
OD
setting for each LVDS output buffer.
Assignment Name
Assignment Name
Assignment Name
Transmitter
OD
LVDS
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Settings in Quartus II Software Assignment Editor
Z
Z
OD
0
0
= 50 Ω
= 50 Ω
OD
in the Quartus II software Assignment Editor.
)
D
OCT support for LVDS input buffers in the
Receiver with On-Chip
Arria II GX Differential
100 Ω Termination
R
D
0,1
2
Differential
Table 8–4
Assignment Value
Assignment Value
Assignment Value
© July 2010 Altera Corporation
lists the assignment
Differential I/O Termination
Figure 8–1 on