EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 72

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–12
Round and Saturation Stage
Second Adder and Output Registers
Arria II GX Device Handbook, Volume 1
1
1
1
You can use the chained-output adder at the same time as a second-level adder in
chained output summation mode.
The output of the second-stage adder has the option to go into the round and
saturation logic unit or the output register.
You cannot use the second-stage adder independently from the multiplier and
first-stage adder.
Round and saturation logic units are located at the output of the 44-bit second-stage
adder (the round logic unit followed by the saturation logic unit). There are two
round and saturation logic units per half-DSP block. The input to the round and
saturation logic unit can come from one of the following stages:
■
■
■
■
These stages are described in detail in
page
The round and saturation logic unit is controlled by the dynamic round and saturate
signals, respectively. A logic 1 value on the round signal, saturate signal, or both
enables the round logic unit, saturate logic unit, or both.
You can use the round and saturation logic units together or independently.
The second adder register and output register banks are two banks of 44-bit registers
that can also be combined to form larger 72-bit banks to support 36 × 36 output
results.
The outputs of the different stages in the Arria II GX devices are routed to the output
registers through an output selection unit. Depending on the operational mode of the
DSP block, the output selection unit selects whether the outputs of the DSP blocks
comes from the outputs of the multiplier block, first-stage adder, pipeline registers,
second-stage adder, or the round and saturation logic unit. Based on the DSP block
operational mode you specify, the output selection unit is automatically set by the
software, and has the option to either drive or bypass the output registers. The
exception is when the block is used in shift mode, in which case you dynamically
controls the output-select multiplexer directly.
Output of the multiplier (independent multiply mode in 18 × 18)
Output of the first-stage adder (two-multiplier adder)
Output of the pipeline registers
Output of the second-stage adder (four-multiplier adder, multiply-accumulate
mode in 18 × 18)
4–13.
“Operational Mode Descriptions” on
Chapter 4: DSP Blocks in Arria II GX Devices
DSP Block Resource Descriptions
© July 2010 Altera Corporation