EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 178

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–20
Phase Offset Control
Arria II GX Device Handbook, Volume 1
f
f
Table 7–5. Arria II GX DLL Frequency Modes
For the frequency range of each mode, refer to the
For a 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The
Quartus II software automatically sets the DQ input delay chains so that the skew
between the DQ and DQS/CQ pin at the DQ IOE registers is negligible when the 0°
shift is implemented. You can feed the DQS delay settings to the DQS logic block and
the logic array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the
DQ pins. The signal can also go into the logic array for resynchronization if you are
not using the IOE resynchronization registers. The shifted CQn signal can go to the
negative-edge input register in the DQ IOE or the logic array and is only used for
QDR II+/QDR II SRAM interfaces.
Each DLL has two phase offset modules and can provide two separate DQS delay
settings with independent offset; one offset goes clockwise half-way around the chip
and the other goes counter-clockwise half-way around the chip. Even though you
have independent phase offset control, the frequency of the interface with the same
DLL has to be the same. Use the phase offset control module for making small shifts to
the input signal and use the DQS phase-shift circuitry for larger signal shifts. For
example, if the DLL only offers a multiple of 30° phase shift, but your interface must
have a 67.5° phase shift on the DQS signal, you can use two delay chains in the DQS
logic blocks to give you a 60° phase shift and use the phase offset control feature to
implement the extra 7.5° phase shift.
You can either use a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in 2s:
complement in Gray-code between settings –64 to +63 for frequency mode 0, 1, 2, and
3, and between the –32 to +31 settings for frequency modes 4 and 5. An additional bit
indicates whether the setting has a positive or negative value. The settings are linear,
each phase offset setting adds a delay amount.
For more information about the specified phase-shift settings, refer to the
Device
The DQS phase shift is the sum of the DLL delay settings and the user-selected phase
offset settings whose top setting is 64 for frequency modes 0, 1, 2, and 3; and 32 for
frequency modes 4 and 5. Therefore, the actual physical offset setting range is 64 or 32
subtracted by the DQS delay settings from the DLL.
Frequency Mode
Datasheet.
0
1
2
3
4
5
Available Phase Shift
22.5, 45, 67.5, 90
36, 72, 108, 144
45, 90, 135, 180
36, 72, 108, 144
30, 60, 90, 120
30, 60, 90, 120
Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX Devices
Arria II GX External Memory Interface Features
Number of Delay Chains
© July 2010 Altera Corporation
Datasheet.
16
12
10
12
10
8
Arria II GX