EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 156

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–22
I/O Bank Restrictions
Arria II GX Device Handbook, Volume 1
f
Arria II GX R
optimizing OCT for use in typical transmission line environments, the R
must be equal to or less than the transmission line impedance for optimal
performance. In ideal applications, setting the OCT impedance to match the
transmission line impedance avoids reflections. Alternatively, you can use external
pull-up resistors to terminate the voltage-referenced I/O standards such as SSTL and
HSTL.
Differential I/O Standards
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the signal line. Arria II GX devices provide an optional differential
on-chip resistor when you use LVDS.
For PCB layout guidelines, refer to
AN 315: Guidelines for Designing High Speed FPGA
Each I/O bank can simultaneously support multiple I/O standards. The following
sections provide guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Arria II GX devices.
Non-Voltage-Referenced Standards
Each Arria II GX device I/O bank has its own VCCIO pins and supports only one
V
any number of input signals with different I/O standard assignments, as shown in
Table 6–1 on page
For output signals, a single I/O bank supports non-voltage-referenced output signals
that drive at the same voltage as V
value, it can only drive out the value for non-voltage-referenced signals. For example,
an I/O bank with a 2.5-V V
and 3.0-V LVCMOS inputs (but not output or bidirectional pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each user I/O bank of the
Arria II GX device has a dedicated VREF pin. Each bank can only have a single V
voltage level and a single V
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards use the same
V
Voltage-referenced bidirectional and output signals must be the same as the V
voltage of the I/O bank. For example, you can only place SSTL-2 output pins in an
I/O bank with a 2.5-V V
CCIO
REF
setting.
, either 1.2, 1.5, 1.8, 2.5, 3.0, or 3.3 V. An I/O bank can simultaneously support
S
OCT provides the convenience of no external components. When
6–2.
CCIO
CCIO
REF
.
voltage level at a given time.
setting can support 2.5-V standard inputs and outputs
CCIO
AN 224: High-Speed Board Layout Guidelines
. Because an I/O bank can only have one V
PCBs.
Chapter 6: I/O Features in Arria II GX Devices
Arria II GX Design Considerations
© July 2010 Altera Corporation
S
impedance
CCIO
and
CCIO
CCIO