EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 176

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–18
Arria II GX Device Handbook, Volume 1
1
1
Arria II GX devices support PLL cascading. If you are cascading PLLs, you must use
PLLs adjacent to each other (for example, PLL5 and PLL6) so that the dedicated path
between the two PLLs is used instead of using a global clock (GCLK) or regional clock
(RCLK) network that might be subjected to core noise. The TimeQuest Timing
Analyzer takes PLL cascading into consideration for timing analysis.
Table 7–4. DLL Reference Clock Input
If you are using the ALTMEMPHY megafunction or UniPHY IP core, Altera
recommends using the dedicated PLL input pin for the PLL reference clock.
Figure 7–12
reference clock goes into the DLL to a chain of up to 16 delay elements. The phase
comparator compares the signal coming out of the end of the delay chain block to the
input reference clock. The phase comparator then issues the upndn signal to the
Gray-coded counter. This signal increments or decrements a 6-bit delay setting
(DQS delay settings) that increases or decreases the delay through the delay element
chain to bring the input reference clock and the signals coming out of the delay
element chain in phase.
DLL0
DLL1
Note to
(1) CLK4 to CLK7 are located on the bottom side, CLK8 to CLK11 are located on the right side, and CLK12 to
CLK15 are located on the top side of the device.
Table
DLL
7–4:
shows a simple block diagram of the DQS phase-shift circuitry. The input
(Top/Bottom)
CLK12
CLK13
CLK14
CLK15
CLKIN
CLK4
CLK5
CLK6
CLK7
(Note 1)
Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX External Memory Interface Features
CLK10
CLK11
(Right)
CLKIN
CLK8
CLK9
—
© July 2010 Altera Corporation
PLL1
PLL3
PLL