EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 19

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Arria II GX Device Family Overview
Arria II GX Device Architecture
High-Speed Transceiver Features
© July 2010 Altera Corporation
Arria II GX devices integrate up to 16 transceivers on a single device. The transceiver
block is optimized for cost and power consumption. Arria II GX transceivers support
the following features:
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Configurable pre-emphasis and equalization, and adjustable output differential
voltage
Flexible and easy-to-configure transceiver datapath to implement proprietary
protocols
Signal integrity features
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Diagnostic features
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Programmable transmitter pre-emphasis to compensate for inter-symbol
interference (ISI)
User-controlled five-stage receiver equalization with up to 7 dB of
high-frequency gain
On-die power supply regulators for transmitter and receiver PLL charge pump
and voltage-controlled oscillator (VCO) for superior noise immunity
Calibration circuitry for transmitter and receiver on-chip termination (OCT)
resistors
Serial loopback from the transmitter serializer to the receiver CDR for
transceiver physical coding sublayer (PCS) and physical media attachment
(PMA) diagnostics
Parallel loopback from the transmitter PCS to the receiver PCS with built-in self
test (BIST) pattern generator and verifier
Reverse serial loopback pre- and post-CDR to transmitter buffer for physical
link diagnostics
Loopback master and slave capability in PCIe hard IP blocks
Support for protocol features such as MSB-to-LSB transmission in a
SONET/SDH configuration and spread-spectrum clocking in a PCIe
configuration
Arria II GX Device Handbook, Volume 1
1–5