EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 47

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Arria II GX Devices
Memory Modes
Mixed Width Support
Asynchronous Clear
Figure 3–7. Output Latch Asynchronous Clear Waveform
Memory Modes
© November 2009
aclr at latch
outclk
aclr
q
f
1
Altera Corporation
M9K memory blocks support mixed data widths inherently. MLABs can support
mixed data widths through emulation with the Quartus II software. When using
simple dual-port, true dual-port, or FIFO modes, mixed width support allows you to
read and write different data widths to a memory block. For more information about
the different widths supported per memory mode, refer to
page
Arria II GX memory blocks support asynchronous clears on the output latches and
output registers. Therefore, if your RAM is not using output registers, you can still
clear the RAM outputs using the output latch asynchronous clear.
functional waveform showing this functionality.
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard Plug-In Manager.
For more information about the RAM MegaWizard Plug-In Manager, refer to the
RAM Megafunction User
Arria II GX memory blocks allow you to implement fully synchronous SRAM
memory in multiple modes of operation. M9K blocks do not support asynchronous
memory (unregistered inputs). MLABs support asynchronous (flow-through) read
operations.
Depending on which memory block you target, you can use the following modes:
■
■
■
■
■
■
To choose the desired read-during-write behavior, set the read-during-write behavior
to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager
in the Quartus II software. For more information about this behavior, refer to
“Read-During-Write” on page
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
3–7.
Guide.
3–17.
Arria II GX Device Handbook, Volume 1
“Memory Modes” on
Figure 3–7
shows a
3–7