EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 255
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Device Configuration Pins
Table 9–10. Arria II GX Configuration Pin Summary (Part 2 of 2)
© July 2010
TDO
CRC_ERROR
DATA0
DATA[7..1]
INIT_DONE
CLKUSR
nSTATUS
nCE
CONF_DONE
nCONFIG
ASDO
nCSO
DCLK
nIO_PULLUP
nCEO
MSEL[3..0]
Notes to
(1) Although the nIO_PULLUP is powered up by V
pull-down resistor.
Table
Description
Altera Corporation
9–10:
Input/Output
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
CC
, Altera recommends connecting this pin to V
Dedicated
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
Powered By
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
V
V
V
V
V
V
V
V
V
V
V
V
CCIO
CC
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
C CPD
(1)
or GND directly without using a pull-up or
Arria II GX Device Handbook, Volume 1
All modes except JTAG
Configuration Mode
Optional, all modes
Optional, all modes
All modes
All modes
All modes
All modes
All modes
All modes
All modes
Optional
PS, FPP
JTAG
FPP
AS
AS
AS
9–35
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