EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 180

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–22
Figure 7–14. DQS Update Enable Waveform
Arria II GX Device Handbook, Volume 1
(Updated every 8 cycles)
DQS Delay Settings
Update Enable
Circuitry Output
System Clock
DLL Counter Update
(Every 8 cycles)
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input
DQS/CQ and CQn signals to be shifted by the amount specified by the DQS
phase-shift circuitry or the logic array. There are four delay elements in the DQS delay
chain; the first delay chain closest to the DQS/CQ or CQn pin can either be shifted by
the DQS delay settings or by the sum of the DQS/CQ delay setting and the
phase-offset setting. The number of delay chains required is transparent because the
ALTMEMPHY megafunction and UniPHY IP core automatically set it when you
choose the operating frequency. The DQS delay settings can come from the DQS
phase-shift circuitry on either end of the I/O banks or from the logic array.
The delay elements in the DQS logic block have the same characteristics as the delay
elements in the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own Gray-coded 6-bit or 5-bit settings with the
dqs_delayctrlin[5..0] signals available in the ALTMEMPHY megafunction
and UniPHY IP core. These settings control 1, 2, 3, or all 4 delay elements in the DQS
delay chains. The ALTMEMPHY megafunction and UniPHY IP core can also
dynamically choose the number of DQS delay chains needed for the system. The
amount of delay is equal to the sum of the delay element’s intrinsic delay and the
product of the number of delay steps and the value of the delay steps.
You can also bypass the DQS delay chain to achieve a 0° phase shift.
Update Enable Circuitry
Both the DQS delay settings and the phase-offset settings pass through a register
before going into the DQS delay chains. The registers are controlled by the update
enable circuitry to allow enough time for any changes in the DQS delay setting bits to
arrive at all the delay elements. This allows them to be adjusted at the same time. The
update enable circuitry enables the registers to allow enough time for the DQS delay
settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic
blocks before the next change. It uses the input reference clock or a user clock from the
core to generate the update enable output. The ALTMEMPHY megafunction and
UniPHY IP core use this circuit by default.
of the update enable circuitry output.
6 bit
Chapter 7: External Memory Interfaces in Arria II GX Devices
Figure 7–14
DLL Counter Update
(Every 8 cycles)
Arria II GX External Memory Interface Features
shows an example waveform
© July 2010 Altera Corporation