EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 73

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II GX Devices
Operational Mode Descriptions
Operational Mode Descriptions
Independent Multiplier Modes
© July 2010
Altera Corporation
When the DSP block is configured in chained cascaded output mode, both of the
second-stage adders are used. The first adder is used for performing four-multiplier
adder and the second is used for the chainout adder. The outputs of the
four-multiplier adder are routed to the second-stage adder registers before it enters
the chainout adder. The output of the chainout adder goes to the regular output
register bank. Depending on the configuration, you can route the chainout results to
the input of the next half block’s chainout adder input or to the general fabric
(functioning as regular output registers).
You can only connect the chainin port to the chainout port of the previous DSP
block; it must not be connected to general routings.
The second-stage and output registers are triggered by the positive edge of the clock
signal and are cleared on power up. The following DSP block signals control the
output registers in the DSP block:
■
■
■
This section describes the operation modes of Arria II GX devices.
In independent input and output multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers.
9-Bit, 12-Bit, and 18-Bit Multiplier
You can configure each DSP block multiplier for 9-bit, 12-bit, or 18-bit multiplication.
A single DSP block can support up to eight individual 9 × 9 multipliers, six 12 × 12
multipliers, or up to four individual 18 × 18 multipliers. For operand widths up to
9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a
12 × 12 multiplier is implemented and for operand widths from 13 to 18 bits, an
18 × 18 multiplier is implemented. This is done by the Quartus II software by zero
padding the LSBs.
independent multiplier operation mode. A list of DSP block dynamic signals is shown
in
Table 4–9 on page
clock[3..0]
ena[3..0]
aclr[3..0]
Figure
4–30.
4–6,
Figure
4–7, and
Figure 4–8
show the DSP block in the
Arria II GX Device Handbook, Volume 1
4–13