EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 52

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–12
Arria II GX Device Handbook, Volume 1
Figure 3–14. Arria II GX True Dual-Port Memory
Note to
(1) True dual-port memory supports input and output clock mode in addition to the independent clock mode shown.
The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit
(×18-bit with parity).
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
configurations in true dual-port mode.
Table 3–5. Arria II GX M9K Block Mixed-Width Configuration
In true dual-port mode, M9K blocks support separate write-enable and read-enable
signals. Read-during-write operations to the same address can either output new data
at that location or old data.
In true dual-port mode, you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. No conflict resolution circuitry is built into the
Arria II GX memory blocks. You must handle address conflicts external to the RAM
block.
Figure 3–15
and read operation at port B with the Read-During-Write behavior set to new data.
Registering the RAM’s outputs would simply delay the q outputs by one clock cycle.
8K×1
4K×2
2K×4
1K×8
512×16
1K×9
512×18
Figure
Read Port
3–14:
shows true dual-port timing waveforms for the write operation at port A
8K×1
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
enable_a
rden_a
aclr_a
q_a[]
v
v
v
v
v
—
—
Table 3–5
clock_a
4K×2
v
v
v
v
v
—
—
lists the possible M9K block mixed-port width
(Note 1)
2K×4
v
v
v
v
v
—
—
addressstall_b
address_b[]
byteena_b[]
Chapter 3: Memory Blocks in Arria II GX Devices
Write Port
enable_b
data_b[ ]
clock_b
wren_b
rden_b
aclr_b
1K×8
q_b[]
v
v
v
v
v
—
—
© November 2009 Altera Corporation
512×16
v
v
v
v
v
—
—
1K×9
v
v
—
—
—
—
—
Memory Modes
512×18
v
v
—
—
—
—
—