EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 114

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–22
Post-Scale Counter Cascading
Programmable Duty Cycle
Arria II GX Device Handbook, Volume 1
1
Arria II GX PLLs support post-scale counter cascading to create counters larger than
512. This is automatically implemented in the Quartus II software by feeding the
output of one C counter into the input of the next C counter, as shown in
Figure 5–17. Counter Cascading
Note to
(1) n = 6
When cascading post-scale counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter with the
product of the individual counter settings. For example, if C0 = 40 and C1 = 20, the
cascaded value is C0  C1 = 800.
Post-scale counter cascading is set in the configuration file. You cannot accomplish
post-scale counter cascading with PLL reconfiguration.
The programmable duty cycle allows the PLLs to generate clock outputs with a
variable duty cycle. This feature is supported on the PLL post-scale counters. The
duty-cycle setting is achieved by a low and high time-count setting for the post-scale
counters. The Quartus II software uses the frequency input and the required multiply
or divide rate to determine the duty cycle choices. The post-scale counter value
determines the precision of the duty cycle. The precision is defined by 50% divided by
the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are
possible for duty-cycle choices between 5% to 90%.
Combining the programmable duty cycle with programmable phase shift allows the
generation of precise non-overlapping clocks.
Figure
5–17:
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
C0
C1
C2
C3
C4
Cn
(1)
from preceding
post-scale counter
© July 2010 Altera Corporation
PLLs in Arria II GX Devices
Figure
5–17.