EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 198

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–14
Figure 8–11. Receiver Datapath in Non-DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively.
(3) The rx_out port has a maximum data width of 10.
Arria II GX Device Handbook, Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
Figure
rx_out
8–11:
1
10
The Quartus
add to each trace. You can use the recommended trace delay numbers published
under the LVDS Transmitter/Receiver Package Skew Compensation panel and
manually compensate the skew on the PCB board trace to reduce the
channel-to-channel skews, thus meeting the timing budget between LVDS channels.
For more information about the LVDS Transmitter/Receiver Package Skew
Compensation report panel, refer to the “Arria II GX LVDS Package Skew
Compensation Report Panel“section in the
Megafunction User
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
®
II software Fitter Report panel reports the amount of delay you need to
IOE
Center/Corner PLL
Guide.
2
3
DOUT DIN
(Note
Multiplexer
Bit Slip
Clock
(LVDS_LOAD_EN,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
LVDS_diffioclk,
rx_outclk)
diffioclk
1), (2),
(3)
rx_inclock
SERDES Transmitter/Receiver (ALTLVDS)
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
N
3
(DPA_LO
DPA_diffioclk,
P P
rx_divfwdclk)
P P
© July 2010 Altera Corporation
AD_EN,
DPA Circuitr
DPA Cloc
Retimed
LVDS Clock Domain
P P
P P
Data
k
Differential Receiver
DIN
y
+
rx_in