EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 112

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–20
Arria II GX Device Handbook, Volume 1
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock-output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software TimeQuest Timing Analyzer reports any phase
difference between the two. In normal mode, the delay introduced by the GCLK or
RCLK network is fully compensated.
PLL clocks’ phase relationship in normal mode.
Figure 5–15. Phase Relationship Between PLL Clocks in Normal Mode
Note to
(1) The external clock output can lead or lag the PLL internal clock signals.
Zero-Delay Buffer Mode
In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with
the clock input pin for zero delay through the device. When you use this mode, you
must use the same I/O standard on the input and output clocks to guarantee clock
alignment at the input and output pins. Zero-delay buffer mode is supported on all
Arria II GX PLLs.
Figure
Dedicated PLL Clock Outputs (1)
5–15:
Register Clock Port
PLL Clock at the
PLL Reference
Clock at the
Input Pin
Phase Aligned
Figure 5–15
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
shows an example waveform of the
© July 2010 Altera Corporation
PLLs in Arria II GX Devices