EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 153

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II GX Devices
Arria II GX Termination Schemes for I/O Standards
Figure 6–13. Arria II GX RSDS I/O Standard Termination
Note to
(1) R
© July 2010 Altera Corporation
p
Termination
= 170  and R
Termination
On-Board
Figure
External
OCT
6–13:
s
= 120  for RSDS_E_1R and RSDS_E3R.
Transmitter
Transmitter
Arria II GX devices support DC-coupled LVPECL if the LVPECL output common
mode voltage is in the Arria II GX LVPECL input buffer specification (see
Figure
Figure 6–12. LVPECL DC-Coupled Termination
RSDS
Arria II GX devices support the RSDS output standard with a data rate of up to
360 Mbps with LVDS output buffer types. Arria II GX devices supports true RSDS,
RSDS with a one-resistor network, and RSDS with a three-resistor network. Two
single-ended output buffers are used for external one- or three-resistor networks, as
shown in
A resistor network is required to attenuate the LVDS output-voltage swing to meet
RSDS specifications. You can modify the three-resistor network values to reduce
power or improve the noise margin. The resistor values chosen should satisfy the
equation shown in
One-Resistor Network (RSDS_E_1R)
6–12).
Figure
≤1 inch
Output Buffer
≤1 inch
LVPECL
R P
R P
6–13.
50 Ω
50 Ω
50 Ω
50 Ω
Equation
100 Ω
100 Ω
Arria II GX OCT
Receiver
Receiver
6–1.
(Note 1)
Z
Z
O
O
= 50 Ω
= 50 Ω
Transmitter
Transmitter
Three-Resistor Network (RSDS_E_3R)
100 Ω
R S
R S
R S
≤1 inch
R S
≤
1 inch
LVPECL Input Buffer
R P
R P
Arria II GX Device Handbook, Volume 1
Arria II GX
50
50 Ω
50
50 Ω
100 Ω
100
Arria II GX OCT
Ω
Receiver
Receiver
6–19