EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 298

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

11–4
Table 11–2. 32-Bit Arria II GX Device IDCODE
EXTEST_PULSE
EXTEST_TRAIN
Arria II GX Device Handbook, Volume 1
Notes to
(1) The MSB is on the left.
(2) The IDCODE LSB is always 1.
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX95
Device
Table
11–2:
1
1
Table 11–2
If the device is in the RESET state, when the nCONFIG or nSTATUS signal is low, the
device IDCODE might not be read correctly. To read the device IDCODE correctly, you
must issue the IDCODE JTAG instruction only when the nSTATUS signal is high.
IEEE Std.1149.6 mandates the addition of two new instructions: EXTEST_PULSE and
EXTEST_TRAIN. These two instructions enable edge-detecting behavior on the signal
path containing the HSSI pins. These instructions implement new test behaviors for
HSSI pins and simultaneously behave identically to the IEEE Std. 1149.1 EXTEST
instruction for non-HSSI pins.
The instruction code for EXTEST_PULSE is 0010001111. The EXTEST_PULSE
instruction generates three output transitions:
■
■
■
If you use DC-coupling on the HSSI signals, you must execute the EXTEST
instruction. If you use AC-coupling on the HSSI signal, you must execute the
EXTEST_PULSE instruction.
The instruction code for EXTEST_TRAIN is 0001001111. The EXTEST_TRAIN
instruction behaves like the EXTEST_PULSE instruction with one exception: the
output continues to toggle on the TCK falling edge as long as the TAP controller is in
the RUN_TEST/IDLE state.
Driver drives data on the falling edge of TCK in UPDATE_IR/DR.
Driver drives inverted data on the falling edge of TCK after entering the
RUN_TEST/IDLE state.
Driver drives data on the falling edge of TCK after leaving the RUN_TEST/IDLE
state.
Version
(4 Bits)
0000
0000
0000
0000
0000
0000
lists the IDCODE information for Arria II GX devices.
0010010100010010
0010010100000010
0010010100010011
0010010100000011
0010010100010100
0010010100000100
Part Number
(16 Bits)
IDCODE (32 Bits)
(1)
Manufacturer Identity
Chapter 11: JTAG Boundary-Scan Testing
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
(11 Bits)
© July 2010 Altera Corporation
BST Operation Control
(1 Bit)
LSB
1
1
1
1
1
1
(2)