EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 154

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–20
Arria II GX Device Handbook, Volume 1
f
1
Equation 6–1.
To validate that custom resistor values meet the RSDS requirements, Altera
recommends performing additional simulations with IBIS models.
For more information about the RSDS I/O standard, refer to the RSDS Specification
from the National Semiconductor website at www.national.com.
mini-LVDS
Arria II GX devices support the mini-LVDS output standard with a data rate up to
400 Mbps with LVDS-type output buffers. Arria II GX devices support true
mini-LVDS with a three-resistor network. Two single-ended output buffers are used
for external three-resistor networks, as shown in
Figure 6–14. Arria II GX mini-LVDS I/O Standard Termination
Note to
(1) R
p
= 170  and R
Figure
6–14:
Termination
Termination
On-Board
External
OCT
s
= 120  for mini-LVDS_E_3R.
Transmitter
Transmitter
R
Three-Resistor Network (mini-LVDS_E_3R)
R
S x
S +
R S
R S
1 inch
R S
R S
R
1 inch
2
R
P
2
R
P
P
R
P
= 50 Ω
50
50 
Figure
Arria II GX Termination Schemes for I/O Standards
50 
50 
Chapter 6: I/O Features in Arria II GX Devices
100 
(Note 1)
6–14.
100

Arria II GX OCT
© July 2010 Altera Corporation
Receiver
Receiver