EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 193

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Receiver
Differential Receiver
Figure 8–6. LVDS Receiver Block Diagram
Notes to
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively.
(2) The rx_out port has a maximum data width of 10.
© July 2010
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Altera Corporation
8–6:
10
Figure 8–6
The center/corner PLL receives the external reference clock input (rx_inclock) and
generates eight different phases of the same clock. The DPA block chooses one of the
eight clock phases from the center/corner PLL and aligns to the incoming data to
maximize receiver skew margin. The synchronizer circuit is a 1-bit wide by 6-bit deep
FIFO buffer that compensates for any phase difference between the DPA block and the
deserializer. If necessary, the user-controlled data realignment circuitry inserts a single
bit of latency in the serial bit stream to align to the word boundary. The deserializer
converts the serial data to parallel data and sends the parallel data to the FPGA fabric.
The physical medium connecting the LVDS transmitter and the receiver channels may
introduce skew between the serial data and the source synchronous clock. The
instantaneous skew between each LVDS channel and the clock also varies with the
jitter on the data and clock signals, as seen by the receiver.
Arria II GX devices support the following receiver modes to overcome skew between
the source-synchronous or reference clock and the received serial data:
■
■
■
IOE Supports SDR, DDR, or Non-Registered Datapath
Non-DPA mode
DPA mode
Soft clock data recovery (CDR) mode
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows a block diagram of an LVDS receiver in the right I/O bank.
IOE
Center/Corner PLL
(Note
2
3
1),
DOUT DIN
Multiplexer
Bit Slip
Clock
(LVDS_LOAD_EN,
(2)
LVDS_diffioclk,
rx_outclk)
diffioclk
rx_inclock
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
LVDS Receiver
3
(DPA_LOAD_EN,
Arria II GX Device Handbook, Volume 1
DPA_diffioclk,
rx_divfwdclk)
DPA Circuitry
Retimed
DPA Clock
Data
DIN
LVDS Clock Domain
DPA Clock Domain
+
rx_in
8–9