EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 243

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Passive Serial Configuration
Figure 9–11. Multi-Device PS Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to
© July 2010
to meet the V
system's I/Os with V
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR
Altera Corporation
9–11:
IH
Memory
specification of the I/O standard on the device and the external host. Altera recommends that you power up the configuration
DATA[0]
CCIO
The Arria II GX device receives configuration data on the DATA0 pin and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using configuration data in .rbf, .hex, or .ttf format, you must send the LSB of
each data byte first. For example, if the .rbf file contains the byte sequence 02 1B EE 01
FA, the serial bitstream you should transmit to the device is 0100-0000 1101-1000
0111-0111 1000-0000 0101-1111.
Figure 9–11
circuit is similar to the PS configuration circuit for a single device, except Arria II GX
devices are cascaded for multi-device configuration.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device’s nCE pin, which prompts the
second device to begin configuration. The second device in the chain begins
configuration in one clock cycle. Therefore, the transfer of data destinations is
transparent to the MAX II device or microprocessor. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device
in the chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
Because all nSTATUS and CONF_DONE pins are tied together, if any device detects an
error, configuration stops for the entire chain and you must reconfigure the entire
chain. For example, if the first device flags an error on nSTATUS, it resets the chain by
pulling its nSTATUS pin low. This behavior is similar to a single device detecting an
error.
for I/O bank 3C.
V
CCIO (1)
shows how to configure multiple devices using an external host. This
10 k Ω
V
CCIO (1)
10 k Ω
GND
DATA[0]
Arria II GX Device 1
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
MSEL[3..0]
nCEO
(2)
V
CCIO (1)
10 kΩ
Arria II GX Device Handbook, Volume 1
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Arria II GX Device 2
CCIO
MSEL[3..0]
must be high enough
Table
nCEO
9–2.
N.C.
(2)
9–23