EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 246

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–26
Table 9–7. PS Timing Parameters for Arria II GX Devices (Part 2 of 2)—Preliminary
PS Configuration Using a Download Cable
Arria II GX Device Handbook, Volume 1
t
t
t
t
t
Notes to
(1) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
R
CD2UM
CD2CU
CD2UMC
Symbol
Table
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
f
9–7:
1
For more information about device configuration options and how to create
configuration files, refer to the
Formats
In this section, the generic term “download cable” includes the Altera USB-Blaster
universal serial bus (USB) port download cable, ByteBlaster II parallel port download
cable, ByteBlasterMV
cable.
In a PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the Arria II GX device using the download
cable.
During configuration, the programming hardware or download cable places the
configuration data one bit at a time on the device’s DATA0 pin. The configuration data
is clocked into the target device until CONF_DONE goes high.
When using a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart the
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no affect on the device
initialization because this option is disabled in the .sof when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you are not required to provide a clock on CLKUSR pin when you
are configuring the device with the Quartus II programmer and a download cable.
chapters in volume 2 of the Configuration Handbook.
Parameter
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
(2)
TM
parallel port download cable, and EthernetBlaster download
Device Configuration Options
4 × maximum
t
DCLK period
CD2CU
Minimum
CLKUSR
period)
—
—
55
+ (8532
and
Maximum
© July 2010 Altera Corporation
150
40
40
—
—
Configuration File
Passive Serial Configuration
Units
s
—
—
ns
ns