EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 270

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–50
Figure 9–25. Remote System Upgrade Circuit Data Path
Note to
(1) The RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals are internally controlled
Remote System Upgrade Registers
Table 9–14. Remote System Upgrade Registers (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
Shift register
Control register
by the ALTREMOTE_UPDATE megafunction.
Figure
RU_DOUT
9–25:
dout
Register
Status Register (SR)
Figure 9–25
The remote system upgrade block contains a series of registers that store the page
addresses, watchdog timer settings, and status information. These registers are listed
in
Bit [4..0]
[4..0]
Table
RU_SHIFTnLD
capture
Shift Register
9–14.
din
shows the datapath of the remote system upgrade block.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
RU_CAPTnUPDT
dout
This register is accessible by the logic array and allows the update, status, and
control registers to be written and sampled by user logic.
This register contains the current page address, user watchdog timer settings,
and one bit specifying whether the current configuration is a factory
configuration or an application configuration. During a read operation in an
application configuration, this register is read into the shift register. When a
reconfiguration cycle is initiated, the contents of the update register are written
into the control register.
Control Register
Update Register
Logic Array
Bit [37..0]
[37..0]
[37..0]
Logic Array
clkout
(Note 1)
Logic Array
capture
capture
update
RU_CLK
clkin
din
update
RU_DIN RU_nCONFIG
Description
Internal Oscillator
Machine
State
RSU
Dedicated Remote System Upgrade Circuitry
time-out
© July 2010 Altera Corporation
RU_nRSTIMER
Watchdog
Timer
User