EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 136
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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6–2
Arria II GX I/O Standards Support
Table 6–1. Arria II GX I/O Standards and Voltage Levels
Arria II GX Device Handbook, Volume 1
3.3-V LVTTL/3.3-V LVCMOS
3.0-V LVTTL/3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 Class I and Class II
SSTL-18 Class I and Class II
SSTL-15 Class I
HSTL-18 Class I and Class II
HSTL-15 Class I and Class II
HSTL-12 Class I and Class II
Differential SSTL-2
Differential SSTL-18
Differential SSTL-15
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
LVDS
RSDS and mini-LVDS
LVPECL
BLVDS
Notes to
(1) PCI-X does not meet the PCI-X I-V curve requirement at the linear region.
(2) Single-ended SSTL/HSTL, differential SSTL/HSTL, LVDS, LVPECL, and BLVDS input buffers are powered by V
(3) Differential SSTL/HSTL inputs use LVDS differential input buffers without R
Table
I/O Standard
(1)
f
6–1:
Table 6–1
values for input and output V
For detailed electrical characteristics of each I/O standard, refer to the
Devices
Datasheet.
shows the supported I/O standards for Arria II GX devices and the typical
PCI-X Rev 1.0
PCI Rev 2.2
JESD8-16A
JESD8-16A
JESD8-9B
JESD8-9B
JESD8-11
JESD8-12
JESD8-15
JESD8-15
ANSI/TIA/
Standard
JESD8-B
JESD8-B
JESD8-5
JESD8-7
JESD8-6
JESD8-6
JESD8-6
JESD8-6
Support
EIA-644
—
—
—
—
—
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
Operation
1.8/1.5
1.8/1.5
(2),
(2),
(2),
(2),
(2),
(2),
(Note
Input
CCIO
1.2
3.0
3.0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
—
(3)
(3)
(3)
(3)
(3)
(3)
, V
1),
V
CCPD
CC IO
(2)
D
(V)
OCT support.
, V
Operation
Output
REF
3.3
3.0
1.8
1.5
1.2
3.0
3.0
2.5
1.8
1.5
1.8
1.5
1.2
2.5
1.8
1.5
1.8
1.5
1.2
2.5
2.5
2.5
2.5
—
, and board V
Chapter 6: I/O Features in Arria II GX Devices
V
C CP D
3.3
3.0
2.5
2.5
2.5
3.0
3.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
(V)
TT
.
Arria II GX I/O Standards Support
© July 2010 Altera Corporation
CCPD
V
1.25
0.90
0.75
0.90
0.75
.
REF
0.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(V)
Arria II GX
V
1.25
0.90
0.75
0.90
0.75
1.25
0.90
0.75
0.90
0.75
0.60
TT
0.6
—
—
—
—
—
—
—
—
—
—
—
—
(V)
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