EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 89
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 4: DSP Blocks in Arria II GX Devices
Operational Mode Descriptions
Figure 4–17. Round and Saturation Locations
© July 2010
Altera Corporation
43
43
16 User defined SAT Positions (bit 43-28)
1
42
42
Two saturation modes are supported in Arria II GX devices:
■
■
You must select one of the two options at compile time.
In 2’s complement format, the maximum negative number that can be represented is
–2
maximum negative number to –2
■
■
Table 4–8
36-bits.
Table 4–8. Examples of Saturation
Arria II GX devices have up to 16 configurable bit positions out of the 44-bit bus
([43:0]) for the round and saturate logic unit, providing higher flexibility. You must
select the 16 configurable bit positions at compile time. These 16-bit positions are
located at bits [21:6] for rounding and [43:28] for saturation, as shown in
Figure
For symmetric saturation, the RND bit position is also used to determine where the
LSP for the saturated data is located.
(n–1)
Asymmetric saturation mode
Symmetric saturation mode
Asymmetric 32-bit saturation: Max = 0 × 7FFFFFFF, Min = 0 × 80000000
Symmetric 32-bit saturation: Max = 0 × 7FFFFFFF, Min = 0 × 80000001
44 to 36 Bits Saturation
, and the maximum positive number is 2
4–17.
5926AC01342h
ADA38D2210h
lists how the saturation works. In this example, a 44-bit input is saturated to
29
28
21
16 User defined RND Positions (bit 21-6)
20
Symmetric SAT Result
(n–1)
+ 1. For example, for 32 bits:
800000001h
7FFFFFFFFh
(n–1)
– 1. Symmetrical saturation limits the
7
6
Arria II GX Device Handbook, Volume 1
Asymmetric SAT Result
800000000h
7FFFFFFFFh
1
0
0
4–29
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