EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 185

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

© July 2010
AIIGX51008-3.0
Altera Corporation
This chapter describes the high-speed differential I/O features and resources as well
as the functionality of the serializer/deserializer (SERDES) and dynamic phase
alignment (DPA) circuitry in Arria
in Arria II GX devices allows for high-speed LVDS interface on the top, bottom, and
right sides of the device. The left side of the device is occupied by high-speed
transceiver blocks. Dedicated SERDES and DPA circuitry are implemented on the
right side of the device to further enhance LVDS interface performance in the device.
This chapter contains the following sections:
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Arria II GX devices have the following dedicated circuitry for high-speed differential
I/O support:
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Arria II GX devices support the following differential I/O standards:
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“LVDS Channels” on page 8–2
“LVDS SERDES and DPA Block Diagram” on page 8–5
“Differential Transmitter” on page 8–7
“Differential Receiver” on page 8–9
“Programmable Pre-Emphasis and Programmable V
“Differential I/O Termination” on page 8–18
“PLLs” on page 8–18
“LVDS and DPA Clock Networks” on page 8–19
“Source-Synchronous Timing Budget” on page 8–20
“Differential Pin Placement Guidelines” on page 8–23
“Setting Up an LVDS Transmitter or Receiver Channel” on page 8–33
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
LVDS
mini-LVDS
Reduced swing differential signaling (RSDS)
Low-voltage positive emitter-coupled logic (LVPECL)
Bus LVDS (BLVDS)
8. High-Speed Differential I/O Interfaces
®
II GX devices. The new modular I/O architecture
and DPA in Arria II GX Devices
OD
Arria II GX Device Handbook, Volume 1
.” on page 8–17