EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 232

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–12
Figure 9–4. FPP Configuration Timing Waveform with Decompression and Design Security not Enabled
Notes to
(1) Use this timing waveform when decompression and design security features are not used.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels.
(3) After power up, the Arria II GX device holds nSTATUS low for the time of the POR delay.
(4) After power up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. DATA[0] is
(7) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
Table 9–4. FPP Timing Parameters for Arria II GX Devices with Decompression and Design Security not Enabled
Arria II GX Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
f
t
(Note 1)
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
R
When nCONFIG is pulled low, a reconfiguration cycle begins.
a dedicated pin that is used for both the passive and active configuration modes and is not available as a user I/O pin after configuration.
Figure
(Part 1 of 2)—Preliminary
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Input rise time
9–4:
CONF_DONE (4)
nSTATUS (3)
INIT_DONE
DATA[7..0]
nCONFIG
Table 9–4
when the decompression and design security features are not enabled.
User I/O
DCLK
t
t
CF2CD
CFG
lists the timing parameters for Arria II GX devices for FPP configuration
Parameter
t
CF2ST1
t
CF2ST0
t
t
CF2CK
ST2CK
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
t
Byte 0 Byte 1 Byte 2 Byte 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
Byte n-2 Byte n-1
Minimum
(7)
500
3.2
3.2
—
—
10
—
—
—
Byte n
2
2
4
0
8
t
CD2UM
(6)
Maximum
500
500
Fast Passive Parallel Configuration
800
800
125
© July 2010 Altera Corporation
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—
—
—
—
—
—
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40
User Mode
User Mode
(5)
(2)
(2)
(Note
1),
Units
MHz
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
(2)