EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 235

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Active Serial Configuration (Serial Configuration Devices)
© July 2010
Altera Corporation
f
1
For more information about serial configuration devices, refer to the
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
Serial configuration devices provide a serial interface to access configuration data.
During device configuration, Arria II GX devices read configuration data using the
serial interface, decompress data if necessary, and configure their SRAM cells. This
scheme is referred to as the AS configuration scheme because the Arria II GX device
controls the configuration interface. This scheme contrasts with the PS configuration
scheme, where the configuration device controls the interface.
The Arria II GX decompression and design security features are available when
configuring your Arria II GX device using AS mode.
Serial configuration devices have a four-pin interface: serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and active-low chip select (nCS). This
four-pin interface connects to the Arria II GX device pins, as shown in
Figure 9–6. Single Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Arria II GX devices use the ASDO-to-ASDI path to control the configuration device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To configure MSEL[3..0],
(4) Arria II GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
The serial clock (DCLK) generated by the Arria II GX device controls the entire
configuration cycle and provides timing for the serial interface. During the
configuration, Arria II GX devices use an internal oscillator or an external clock source
to generate DCLK. At the initial stage of configuration cycle, the Arria II GX generates
a default DCLK (40 MHz maximum) from the internal oscillator to read the header
information of the programming data stored in the EPCS. After the header
refer to
Figure
Table
Serial Configuration
9–6:
9–2.
Device
DATA
DCLK
ASDI
nCS
V
CCIO (1)
CCIO
10 kΩ
power supply of bank 3C.
V
CCIO (1)
(2)
10 kΩ
GND
V
CCIO (1)
10 kΩ
nCONFIG
nSTATUS
CONF_DONE
nCE
DATA0
DCLK
nCSO
ASDO
Arria II GX Device
Arria II GX Device Handbook, Volume 1
CLKUSR
MSEL [3..0]
nCEO
Serial
Figure
N.C.
(4)
(3)
9–6.
9–15