EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 196

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–12
Figure 8–8. Data Realignment Timing
Figure 8–9. Receiver Data Re-Alignment Rollover
Deserializer
Arria II GX Device Handbook, Volume 1
rx_channel_data_align
rx_cda_max
rx_outclock
rx_inclock
rx_channel_data_align
Figure 8–8
factor set to 4.
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set to equal to or greater than the deserialization factor, allowing enough depth in
the word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the ALTLVDS megafunction. An optional status signal
(rx_cda_max) is available to the FPGA fabric from each channel to indicate when the
preset rollover point is reached.
Figure 8–9
rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has
occurred.
The deserializer, which includes shift registers and parallel load registers, converts the
serial data from the bit slip to parallel data before sending the data to the FPGA fabric.
The deserialization factor supported is 4, 6, 7, 8, or 10. You can bypass the deserializer
to support DDR (×2) and SDR (×1) operations, as shown in
the DPA and data realignment circuit when the deserializer is bypassed. The IOE
contains two data input registers that can operate in DDR or SDR mode.
rx_outclock
rx_inclock
rx_out
shows receiver output after one bit-slip pulse with the deserialization
shows a preset value of four-bit times before rollover occurs. The
rx_in
3
2
3210
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
1
0
3
2
321x
1
0
3
2
xx21
1
Figure
0
© July 2010 Altera Corporation
0321
8–10. You can use
Differential Receiver