EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 152

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–18
Figure 6–10. Arria II GX LVDS I/O Standard Termination
Note to
(1)
Arria II GX Device Handbook, Volume 1
R
p
= 170
Figure
LVDS_E_3R) (1)

External On-Board
(Single-Ended
OCT Receive
6–10:
LVDS Output
and R
with Three
OCT Receive
Network,
Termination
Resistor
(True LVDS
Termination
Output)
s
= 120
Figure 6–10
Differential LVPECL
Arria II GX devices support the LVPECL I/O standard on input clock pins only.
LVPECL output operation is not supported. LVDS input buffers are used to support
LVPECL input operation. AC-coupling is required when the LVPECL common mode
voltage of the output buffer is higher than Arria II GX LVPECL input common mode
voltage.
used at the receiver end are external to the device.
Figure 6–11. LVPECL AC-Coupled Termination

for LVDS_E_3R.
Figure 6–11
Output Buffer
Single-Ended Outputs
Differential Outputs
Differential Outputs
LVPECL
shows the details of LVDS termination in Arria II GX devices.
shows the AC-coupled termination scheme. The 50- resistors
0.1 μF
0.1 μF
External Resistor
Rs
Rs
(Note 1)
Rp
Z
Z
O
O
= 50 Ω
= 50 Ω
LVDS
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V
ICM
100 Ω
Arria II GX Termination Schemes for I/O Standards
Chapter 6: I/O Features in Arria II GX Devices
100 Ω
100 Ω
50 Ω
50 Ω
LVPECL Input Buffer
Arria II GX
Differential Inputs
Arria II GX OCT
Differential Inputs
Differential Inputs
© July 2010 Altera Corporation
Arria II GX OCT