EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 274

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–54
User Watchdog Timer
Quartus II Software Support
Arria II GX Device Handbook, Volume 1
1
1
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. The system uses the timer to detect functional errors after an
application configuration is successfully loaded into the Arria II GX device.
To allow remote system upgrade dedicated circuitry to reset the watchdog timer, you
must assert the RU_nRSTIMER signal active for a minimum of 250 ns. This is
equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE
megafunction high for a minimum of 250 ns.
The user watchdog timer is a counter that counts down from the initial value loaded
into the remote system upgrade control register by the factory configuration. The
counter is 29-bits wide and has a maximum count value of 2
user watchdog timer value, specify only the most significant 12 bits. The granularity
of the timer setting is 2
10-MHz internal oscillator.
oscillator.
Table 9–18. 10-MHz Internal Oscillator Specifications—Preliminary
The user watchdog timer begins counting after the application configuration enters
device user mode. This timer must be periodically reloaded or reset by the application
configuration before the timer expires by asserting RU_nRSTIMER. If the application
configuration does not reload the user watchdog timer before the count expires, a
time-out signal is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user watchdog
timer status bit (Wd) in the remote system upgrade status register and reconfigures the
device by loading the factory configuration.
During the configuration cycle of the device, the user watchdog timer is not enabled.
Errors during configuration are detected by the CRC engine. Also, the timer is
disabled for factory configurations. Functional errors should not exist in the factory
configuration because it is stored and validated during production and is never
updated remotely.
The user watchdog timer is disabled in factory configurations and during the
configuration cycle of the application configuration. It is enabled after the application
configuration enters user mode.
The Quartus II software provides the flexibility to include the remote system upgrade
interface between the Arria II GX device logic array and the dedicated circuitry,
generates configuration files for production, and allows remote programming of the
system configuration memory.
Minimum
4.3
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
15
cycles. The cycle time is based on the frequency of the
Table 9–18
Typical
5.3
lists the operating range of the 10-MHz internal
Maximum
10
29
. When specifying the
© July 2010 Altera Corporation
Quartus II Software Support
Units
MHz