EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 80

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–20
Two-Multiplier Adder Sum Mode
Figure 4–11. Two-Multiplier Adder Mode Shown for Half-DSP Block
Notes to
(1) In a half-DSP block, you can implement 2 two-multiplier adders.
(2) Block output for accumulator overflow and saturate overflow.
Arria II GX Device Handbook, Volume 1
Figure
4–11:
1
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
In the two-multiplier adder configuration, the DSP block can implement four 18-bit
two-multiplier adders (2 two-multiplier adders per half-DSP block). You can
configure the adders to take the sum or difference of two multiplier outputs.
Summation or subtraction must be selected at compile time. The two-multiplier adder
function is useful for applications such as FFTs, complex FIR, and IIR filters.
Figure 4–11
The loopback mode is a sub-feature of the two-multiplier adder mode.
shows the DSP block configured in the loopback mode. This mode takes the 36-bit
summation result of the two multipliers and feeds back the most significant 18-bits to
the input. The lower 18-bits are discarded. You have the option to disable or zero-out
the loopback data with the dynamic zero_loopback signal. A logic 1 value on
the zero_loopback signal selects the zeroed data or disables the looped back data,
and a logic 0 selects the looped back data.
The option to use the loopback mode or the general two-multiplier adder mode must
be selected at compile time.
clock[3..0]
ena[3..0]
aclr[3..0]
shows the DSP block configured in the two-multiplier adder mode.
Half-DSP Block
output_saturate
output_round
signa
signb
+
(Note 1)
Chapter 4: DSP Blocks in Arria II GX Devices
overflow (2)
© July 2010 Altera Corporation
Operational Mode Descriptions
result[ ]
Figure 4–12